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| ? 2012-2014 microchip technology inc. ds20002298c-page 1 mcp2021a/2a features: ? the mcp2021a/2a are compliant with lin bus specifications version 1.3, 2.1 and with sae j2602-2 ? support baud rates up to 20 kbaud ? 43v load dump protected ? maximum continuous input voltage: 30v ? wide lin-compliant supply voltage: 6.0 ? 18.0v ? extended temperature range: -40 to +125c ? interface to pic ? mcu eusart and standard usarts ? wake-up on lin bus activity or local wake input ? local interconnect network (lin) bus pin: - internal pull-up termination resistor and diode for slave node - protected against v bat shorts - protected against loss of ground - high-current drive ?t xd and lin bus dominant time-out function ? two low-power modes: - transmitter off: 90 a (typical) - power down: 4.5 a (typical) ? output indicating internal reset state (por or sleep wake) ? mcp2021a/2a on-chip voltage regulator: - output voltage of 5.0v or 3.3v at 70 ma capability with tolerances of 3% over the temperature range - internal short circuit current limit - external components limited to filter capacitor and load capacitor ? automatic thermal shutdown ? high electromagnetic immunity (emi), low electromagnetic emission (eme) ? robust esd performance: 15 kv for l bus and v bb pin (iec61000-4-2) ? transient protection for l bus and v bb pins in automotive environment (iso7637) ? meets stringent automotive design requirements, including ?oem hardware requirements for lin, can and flexray interfaces in automotive applications?, version 1.2, march 2011 ? multiple package options, including small 4x4 mm dfn package description: the mcp2021a/2a provide a bidirectional, half-duplex communication physical interface to meet the lin bus specification revision 2.1 and sae j2602-2. the devices incorporate a voltage regulator with 5v or 3.3v at 70 ma regulated power supply output. the devices have been designed to meet the stringent quiescent current requirements of the automotive industry and will survive +4 3 v load dump transients and double battery jumps. package types mcp2021a pdip, soic v reg cs/lwake t xd 1 2 3 4 8 7 6 5 r xd fault /t xe v bb l bus v ss mcp2021a 4x4 dfn v reg cs/lwake t xd r xd fault /t xe v bb l bus v ss 1 2 3 4 8 7 6 5 ep 9 mcp2022a pdip, soic, tssop v reg cs/lwake t xd 1 2 3 4 14 13 12 11 r xd fault /t xe v bb l bus v ss reset 5 10 nc nc 6 9 nc 7 8 nc nc * includes exposed thermal pad (ep), see table 1-2 . lin transceiver with voltage regulator
mcp2021a/2a ds20002298c-page 2 ? 2012-2014 microchip technology inc. mcp2021a/2a block diagram internal circuits v reg fault / t xe r xd t xd cs/lwake bus wake-up slope control v reg 4.2v v reg reset ( mcp2022a only) v bb l bus v ss ~ 30 k ? short circuit protection thermal protection voltage regulator wake-up logic and power control ratiometric reference bus dominant timer thermal and short circuit protection ? 2012-2014 microchip technology inc. ds20002298c-page 3 mcp2021a/2a 1.0 device overview the mcp2021a/2a devices provide a physical interface between a microcontroller and a lin half-duplex bus. they are intended for automotive and industrial applications with serial bus baud rates up to 20 kbaud. these devices will translate the cmos/ttl logic levels to lin logic levels and vice versa. the mcp2021a/2a offer optimum emi and esd performance and can withstand high voltage on the lin bus. the devices support two low-power modes to meet automotive industry power consumption requirements. the mcp2021a/2a also provide a +5v or 3.3v regulated power output at 70 ma. 1.1 modes of operation the mcp2021a/2a work in five modes: power-on reset, power-down, ready, operation and transmitter off. for an overview of all operational modes, please refer to ta b l e 1 - 1 . for the operational mode transition, please refer to figure 1-1 . figure 1-1: state diagram note 1: vreg_ok: regulator output voltage > 0.8v reg _ nom . 2: if the voltage on pin v bb falls below v off , the device will enter power-on reset mode from all other modes, which is not shown in the figure. 3: fault /t xe = 1 represents input high and no fault conditions. fault /t xe = 0 represents input low or a fault condition. refer to table 1-5 . por (2) v reg off rx off tx off ready v reg on rx on tx off tx off v reg on rx on tx off power-down v reg off rx off tx off operation v reg on rx on tx on v bb >v on cs/lwake = 1& fault/t xe = 0& cs/lwake = 0 cs/lwake = 1 & fault/t xe = 1 (3) & t xd = 1& vreg_ok = 1 (1) cs/lwake = 1& fault/t xe = 1 (3) & t xd = 1 cs/lwake = 1& fault/t xe = 0 cs/lwake = 0 cs/lwake = 1 or voltage rising edge on lbus cs/lwake = 0 mcp2021a/2a ds20002298c-page 4 ? 2012-2014 microchip technology inc. 1.1.1 power-on reset mode upon application of v bb or whenever the voltage on v bb is below the threshold of regulator turn-off voltage v off (typically 4.50v), the device enters power-on reset (por) mode. during this mode, the device maintains the digital section in a reset mode and waits until the voltage on the v bb pin rises above the threshold of regulator turn-on voltage v on (typically 5.75v) to enter ready mode. in power-on reset mode, the lin physical layer and voltage regulator are disabled and the reset output ( mcp2022a only) is forced to low. 1.1.2 ready mode the device enters ready mode from por mode after the voltage on v bb rises above the threshold of regulator turn-on voltage v on or from power-down mode when a remote or local wake-up event happens. upon entering ready mode, the voltage regulator and the receiver section of the transceiver are powered up. the transmitter remains in an off state. the device is ready to receive data but not to transmit. in order to minimize the power consumption, the regulator operates in a reduced-power mode. it has a lower gbw product and it is thus slower. however, the 70 ma drive capability is unchanged. the device stays in ready mode until the output of the voltage regulator has stabilized and the cs/lwake pin is high (? 1 ?). 1.1.3 operation mode if v reg is ok (v reg >0.8v reg _ norm ) and the cs/lwake, fault /txe and t xd pins are high, the part enters operation mode from either ready or transmitter off mode . in this mode, all internal modules are operational. the internal pull-up resistor between l bus and v bb is connected only in this mode. the device goes into power-down mode at the falling edge on cs/lwake or into transmitter off mode at the falling edge on fault /t xe while cs/lwake stays high. 1.1.4 transmitter off mode in transmitter off mode, the receiver is enabled but the l bus transmitter is off. it is a lower power mode. in order to minimize power consumption, the regulator operates in a reduced-power mode. it has a lower gbw product and it is thus slower. however, the 70 ma drive capability is unchanged. the transmitter may be re-enabled whenever the fault /t xe signal returns high, by removing the internal fault condition and by driving fault/t xe high. the transmitter will not be enabled even if the fault /t xe pin is brought high externally, when the internal fault is still present. however, externally forcing the fault /t xe high while the internal fault is still present should be avoided, since this will induce high current and power dissipation in the fault /t xe pin. the transmitter is also turned off whenever the voltage regulator is unstable or recovering from a fault. this prevents unwanted disruption of the bus during times of uncertain operation. 1.1.5 power-down mode in power-down mode, the transceiver and the voltage regulator are both off. only the bus wake-up section and the cs/lwake pin wake-up circuits are in operation. this is the lowest power mode. if any bus activity (e.g., a break character) occurs during power-down mode, the device will immediately enter ready mode and enable the voltage regulator. then, once the regulator output has stabilized (approximately 0.3 ms to 1.2 ms), it goes into operation mode. refer to section 1.1.6 ?remote wake-up? . the part will also enter ready mode from power-down mode, followed by the operation mode, if the cs/lwake pin becomes active high (? 1 ?). 1.1.6 remote wake-up the remote wake-up sub-module observes the l bus in order to detect bus activity. in power-down mode, normal lin recessive/dominant threshold is disabled and the lin bus wake-up voltage threshold v wk ( lbus ) is used to detect bus activities. bus activity is detected when the voltage on the l bus falls below the lin bus wake-up voltage threshold v wk ( lbus ) (approximately 3.5v) for at least t bdb (a typical duration of 80 s) followed by a rising edge. such a condition causes the device to leave power-down mode. ? 2012-2014 microchip technology inc. ds20002298c-page 5 mcp2021a/2a table 1-1: overview of operational modes state transmitter receiver internal wake module voltage regulator operation comments por off off off off proceed to ready mode after v bb >v on ready off on off on if cs/lwake is high, then proceed to operation or transmitter off mode. bus off state operation on on off on if cs/lwake is low, then proceed to power-down mode. if fault /t xe is low, then proceed to transmitter off mode. normal operation mode power-down off off on activity detect off on lin bus rising edge or cs/lwake high level, go to ready mode. lowest power mode transmitter off off on off on if cs/lwake is low, then proceed to power-down mode. if fault /t xe is high, then proceed to operation mode. bus off state, lower power mode mcp2021a/2a ds20002298c-page 6 ? 2012-2014 microchip technology inc. 1.2 pin descriptions the descriptions of the pins are listed in tab l e 1 - 2 . 1.2.1 receive data output (r xd ) receive data output pin. the r xd pin is a standard cmos output pin and it follows the state of the l bus pin. 1.2.2 chip select and local wake-up input (cs/lwake) chip select and local wake-up input pin (ttl level, high-voltage tolerant). this pin controls the device state transition. refer to figure 1-1 . if cs/lwake = 1 , the device can work in operation mode (fault /t xe = 1 ) or in transmitter off mode (fault /t xe = 0 ). if cs/lwake = 0 , the device can work in power-down mode or in ready mode. an internal pull-down resistor will keep the cs/lwake pin low to ensure that no disruptive data will be present on the bus while the microcontroller is executing a power-on reset and i/o initialization sequence. when cs/lwake is ? 1 ?, a weak pull-down (~600 k ? ) is used to reduce current. when cs/lwake is ? 0 ?, a stronger pull-down (~300 k ? ) is used to maintain the logic level. this pin may also be used as a local wake-up input (see figure 1-1 ). the microcontroller will set the i/o pin to control the cs/lwake. an external switch or another source can then wake up both the transceiver and the microcontroller. 1.2.3 power output (v reg ) positive supply voltage regulator output pin. an on-chip ldo gives +5.0 or +3.3v at 70 ma regulated voltage on this pin. 1.2.4 transmit data input (t xd ) transmit data input pin (ttl level, hv-compliant, adaptive pull-up). the transmitter reads the data stream on the t xd pin and sends it to the lin bus. the l bus pin is low (dominant) when t xd is low and high (recessive) when t xd is high. t xd is internally pulled up to approximately 4.2v. when t xd is ? 0 ?, a weak pull-up (~900 k ? ) is used to reduce current. when t xd is ? 1 ?, a stronger pull-up (~300 k ? ) is used to maintain the logic level. a series reverse-blocking diode allows applying t xd input voltages greater than the internally generated 4.2v and renders the t xd pin hv-compliant up to 30v (see mcp2021a/2a block diagram ). 1.2.5 reset (mcp2022a only) reset output pin. this pin is open-drain with ~90 k ? pull-up to v reg . it indicates the internal voltage has reached a valid, stable level. as long as the internal voltage is valid (above 0.8 v reg ), this pin will remain high (? 1 ?); otherwise, the reset pin switches to low (? 0 ?). 1.2.6 no connection (nc) no internal connection. table 1-2: pin function table pin name pin number pin type description 8-lead pdip, soic 4x4 dfn 14-lead pdip, soic, tssop r xd 1 1 1 output receive data output cs/lwake 2 2 2 ttl input, hv-tolerant chip select and local wake-up input v reg 3 3 3 output voltage regulator output t xd 4 4 4 input, hv-tolerant transmit data input reset ? ? 5 output reset output nc ? ? 6?10 ? no connection v ss 5 5 11 power ground l bus 6 6 12 i/o, hv lin bus v bb 7 7 13 power battery fault /t xe 8 8 14 i/o, hv-tolerant fault detect output/transmitter enable input ep ? 9 ? ? exposed thermal pad note: cs/lwake should not be tied directly to the v reg pin as this could force the mcp2021a/2a into operation mode before the microcontroller is initialized. ? 2012-2014 microchip technology inc. ds20002298c-page 7 mcp2021a/2a 1.2.7 ground (v ss ) ground pin. 1.2.8 lin bus (l bus ) lin bus pin. l bus is a bidirectional lin bus interface pin and is controlled by the signal t xd . it has an open collector output with a current limitation. to reduce electromagnetic emission, the slopes during signal changes are controlled and the l bus pin has corner-rounding control for both falling and rising edges. the internal lin receiver observes the activities on the lin bus and generates the output signal r xd that follows the state of the l bus . a 1 st degree 160 khz low-pass input filter optimizes electromagnetic immunity. 1.2.9 battery positive supply voltage (v bb ) battery positive supply voltage pin. an external diode is connected in series to prevent the device from being reversely powered (refer to figure 1-7 ). 1.2.10 fault detect output/transmitter enable input (fault /t xe ) fault detect output/transmitter enable input pin. the output section is hv-tolerant open-drain (up to 30v). the input section is identical to the t xd section (ttl level, hv-compliant, adaptive pull-up). the internal pull-up resistor may be too weak for some applications. we recommend adding a 10 k ? external pull-up resistor to ensure a logic high level. its state is defined as shown in tab l e 1 - 5 . the device is placed in transmitter off mode whenever this pin is low (? 0 ?), either from an internal fault condition or by external drive. if cs/lwake is high (? 1 ?), the fault /t xe signals a mismatch between the t xd input and the l bus level. this can be used to detect a bus contention. since the bus exhibits a propagation delay, the sampling of the internal compare is debounced to eliminate false faults. after the device wakes up, the fault /t xe indicates what wakes the device if cs/lwake remains low (? 0 ?) (refer to table 1-5 ). the fault /t xe pin sampled at a rate faster than every 10 s. table 1-3: fault /t xe truth table t xd in r xd out lin bus i/o thermal override fault /t xe definition external input driven output cs = 1 lh v bb off h l fault , t xd driven low, l bus shorted to v bb ( note 1 ) or l bus /t xd permanent dominant detected and trans- mit time-out shutdown. hh v bb off h h ok llgnd off h h ok hlgnd off h h ok , data is being received from l bus xx v bb on h l fault , transceiver in thermal shutdown xx v bb xlx no fault , the cpu is commanding the transceiver to turn off the transmitter driver cs = 0 xx x x x l wake-up from lin bus activity xx x x x h wake-up from por legend: x=don?t care note 1: the fault /t xe is valid after approximately 25 s after the t xd falling edge. this is to eliminate false fault reporting during bus propagation delays. mcp2021a/2a ds20002298c-page 8 ? 2012-2014 microchip technology inc. 1.3 fail-safe features 1.3.1 general fail-safe features ? an internal pull-down resistor on cs/lwake pin disables the transmitter if the pin is floating. ? an internal pull-up resistor on the t xd pin places t xd in high and the l bus in recessive if the t xd pin is floating. ? high-impedance and low-leakage current on l bus during loss of power or ground. ? the current limit on l bus protects the transceiver from being damaged if the pin is shorted to v bb . 1.3.2 thermal protection the thermal protection circuit monitors the die temperature and is able to shut down the lin transmitter and voltage regulator. there are three causes for a thermal overload. a thermal shutdown can be triggered by any one, or a combination of, the following thermal overload conditions: ? voltage regulator overload ? lin bus output overload ? increase in die temperature due to increase in environment temperature the recovery time from the thermal shutdown is equal to adequate cooling time. driving the t xd and checking the r xd pin make it possible to determine whether there is a bus contention (t xd = high, r xd = low) or a thermal overload condition (t xd =low, r xd = high). figure 1-2: thermal shutdown state diagrams 1.3.3 t xd /l bus time-out timer the lin bus can be driven to a dominant level either from the t xd pin or externally. an internal timer deactivates the l bus transmitter if a dominant status (low) on the lin bus lasts longer than bus dominant time-out time, t to ( lin ) (approximately 20 milliseconds). at the same time, the r xd output is put in recessive (high), fault /t xe is also driven to low and the internal lin pull-up resistor is disconnected. the timer is reset on any recessive l bus status or por mode. the recessive status on l bus can be caused either by the bus being externally pulled up or by the t xd pin being returned high. 1.4 internal voltage regulator the mcp2021a/2a have a positive regulator capable of supplying +5.00 or +3.30 v dc 3% at up to 70 ma of load current over the entire operating temperature range of -40c to +125c. the regulator uses a ldo design, is short-circuit-protected and will turn the regulator output off if its output falls below the shutdown voltage threshold, v sd . with a load current of 70 ma, the minimum input to output voltage differential required for the output to remain in regulation is typically +0.5v (+1v maximum over the full operating temperature range). quiescent current is less than 100 a with a full 70 ma load current when the input to output voltage differential is greater than +3.00v. regarding the correlation between v bb , v reg and i dd , please refer to figures 1-4 and 1-5 . when the input voltage (v bb ) drops below the differential needed to provide stable regulation, the voltage regulator output, v reg , will track the input down to approximately v off , at which point the regulator will turn off the output. this will allow pic ? microcontrollers with internal por circuits to generate a clean arming of the por trip point. the mcp2021a/2a will then monitor v bb and turn on the regulator when v bb is above the threshold of regulator turn-on voltage, v on . in power-down mode, the v bb monitor is turned off. under specific ambient temperature and battery voltage range, the voltage regulator can output as high as 150 ma current. for current load capability of the voltage regulator, refer to figures 2-8 and 2-9 . voltage regulator shutdown operation mode transmitter shutdown output overload lin bus shorted to v bb temp < shutdown temp temp < shutdown temp note: the regulator has an overload current limit of approximately 250 ma. the regulator output voltage, v reg , is monitored. if output voltage v reg is lower than v sd , the voltage regulator will turn off. after a recovery time of about 3 ms, the v reg will be checked again. if there is no short circuit (v reg >v sd ), then the voltage regulator remains on. ? 2012-2014 microchip technology inc. ds20002298c-page 9 mcp2021a/2a the regulator requires an external output bypass capacitor for stability. see figure 2-1 for correct capacity and esr for stable operation. in worst-case scenarios, the ceramic capacitor may derate by 50%, based on tolerance, voltage and temperature. therefore, in order to ensure stability, ceramic capacitors smaller than 10 f may require a small series resistance to meet the esr requirements, as shown in tab le 1 -4 . figure 1-3: voltage regulator block diagram note: a ceramic capacitor of at least 10 f or a tantalum capacitor of at least 2.2 f is recommended for stability. table 1-4: recommended series resistance for ceramic capacitors resistance capacitor 1 ? 1f 0.47 ? 2.2 f 0.22 ? 4.7 f 0.1 ? 6.8 f pass element sampling network buffer v reg v bb v ss fast transient loop v ref mcp2021a/2a ds20002298c-page 10 ? 2012-2014 microchip technology inc. figure 1-4: voltage regulator output on power-on reset figure 1-5: voltage regulator ou tput on overcurrent protection note 1: start-up, v bb mcp2021a/2a ds20002298c-page 12 ? 2012-2014 microchip technology inc. equation 1-4 allows lower c bat /c reg values than the 10x ratio we recommend. assume that we have a good quality v bat connection with r tot =0.1 ? and l = 0.1 mh. solving the equation gives c bat /c reg =1. if we increase r tot up to 1 ?? the result becomes c bat /c reg = 1.4. however, if the connection is highly resistive or highly inductive (poor connection), the c bat /c reg ratio greatly increases. figure 1-6 shows the minimum recommended c bat /c reg ratio as a function of the impedance of the v bat connection. figure 1-6: minimum recommended c bat /c reg ratio table 1-5: c bat /c reg ratio by v bat connection type connection type r tot l c bat /c reg ratio good 0.1 ? 0.1 mh 1 typical 1 ? 0.1 mh 1.4 highly inductive 0.1 ? 1mh 7 highly resistive 10 ? 0.1 mh 7 10 c bat /c reg r bat =0.1 r bat =0.3 r bat =1 1 10 0.1 1 c bat /c reg v bat line inductance [mh] r bat =0.1 r bat =0.3 bat r=1 r bat =2 r bat =4 r bat =10 ? 2012-2014 microchip technology inc. ds20002298c-page 13 mcp2021a/2a 1.6 typical applications figure 1-7: typical application circuit figure 1-8: typical li n network configuration lin bus v bb l bus v reg t xd r xd v ss v dd t xd r xd microcontroller v bat c bat c reg cs/lwake i/o fault /t xe i/o 43v ( 5 ) 1k ? v bb master node only v bat 220 k ? wake-up note 1: c reg , the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0 ? 22 f. see figure 2-1 to select the correct esr. 2: c bat is the filter capacitor for the external voltage supply. typically 10 x c reg , with no esr restriction. see figure 1-6 to select the minimum recommended value for c bat . the r tp value is added to the line resistance. 3: this diode is only needed if cs/lwake is connected to the v bat supply. 4: esd protection diode. 5: this component is for additional load dump protection. 6: an external 10 k ? resistor is recommended for some applications. ( 3 ) r tp reset reset v ss i/o ( 6 ) 100 nf mmbz27v ( 4 ) 220 pf lin bus mcp202xa 1k ? v bb 40m + return lin bus lin bus mcp205x lin bus mcp202xa lin bus mcp2003 slave 1 (mcu) slave 2 (mcu) slave n <16 (mcu) master (mcu) mcp2021a/2a ds20002298c-page 14 ? 2012-2014 microchip technology inc. 1.7 icsp? considerations the following should be considered when the mcp2021a/2a are connected to pins supporting in-circuit programming: ? power used for programming the microcontroller can be supplied from the programmer or from the mcp2021a/2a. ? the voltage on the v reg pin should not exceed the maximum value of v reg in dc specifications . ? 2012-2014 microchip technology inc. ds20002298c-page 15 mcp2021a/2a 2.0 electrical characteristics 2.1 absolute maximum ratings? v in dc voltage on r xd and reset ................................................................................................. -0.3v to v reg +0.3 v in dc voltage on t xd , cs/lwake, f ault /t xe ..........................................................................................-0.3 to +40v v bb battery voltage, continuous, non-operating ( note 1 )..............................................................................-0.3 to +40v v bb battery voltage, non-operating (lin bus recessive, no regulator load, t < 60s) ( note 2 ) .......................-0.3 to +43v v bb battery voltage, transient iso 7637 test 1 ................................................................................... ...................-100v v bb battery voltage, transient iso 7637 test 2a .................................................................................. ...................+75v v bb battery voltage, transient iso 7637 test 3a .................................................................................. ..................-150v v bb battery voltage, transient iso 7637 test 3b .................................................................................. .................+100v v lbus bus voltage, continuous....................................................................................................... ................-18 to +30v v lbus bus voltage, transient ( note 3 )............................................................................................................-27 to +43v i lbus bus short circuit current limit ............................................................................................... .....................200 ma esd protection on lin, v bb (iec 61000-4-2) ( note 4 ) .......................................................................................... 15 kv esd protection on lin, v bb (human body model) ( note 5 ).................................................................................... 8 kv esd protection on all other pins (human body model) ( note 5 ) ............................................................................. 4 kv esd protection on all pins (charge device model) ( note 6 ) ................................................................................1500v esd protection on all pins (machine model) ( note 7 ).............................................................................................200v maximum junction temperature ................................................................................................... .......................... 150 ? c storage temperature ............................................................................................................ ...................... -65 to +150 ? c note 1: lin 2.x compliant specification. 2: sae j2602-2 compliant specification. 3: iso 7637/1 load dump compliant (t < 500 ms). 4: according to iec 61000-4-2, 330 ? , 150 pf and transceiver emc test specifications [2] to [4]. 5: according to aec-q100-002/jesd22-a114. 6: according to aec-q100-011b. 7: according to aec-q100-003/jesd22-a115. 2.2 nomenclature used in this document some terms and names used in this data sheet deviate from those referred to in the lin specifications. equivalent values are shown below. ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. exposure to maximum rating conditions for extended periods may affect device reliability. lin 2.1 name term used in the following tables definition v bat not used ecu operating voltage v sup v bb supply voltage at device pin v bus _ lim i sc current limit of driver v busrec v ih (l bus ) recessive state v busdom v il (l bus ) dominant state mcp2021a/2a ds20002298c-page 16 ? 2012-2014 microchip technology inc. 2.3 dc specifications dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for v bb = 6.0v to 18.0v, t a = -40c to +125c, c reg =10f. parameter sym min typ max units conditions power v bb quiescent operating current i bbq ??200ai out =0ma l bus recessive v reg =5.0v ??200ai out =0ma l bus recessive v reg =3.3v v bb ready current i bbrd ??100ai out =0ma l bus recessive v reg =5.0v ??100ai out =0ma l bus recessive v reg =3.3v v bb transmitter-off current i bbto ? ? 100 a with voltage regulator on, transmitter off, receiver on, fault /t xe =v il , cs = v ih , v reg =5.0v ? ? 100 a with voltage regulator on, transmitter off, receiver on, fault /t xe =v il , cs = v ih , v reg =3.3v v bb power-down current i bbpd ? 4.5 8 a with voltage regulator off, receiver on and transmitter off, fault /t xe =v ih , t xd =v ih , cs = v il v bb current with v ss floating i bbnognd -1 ? 1 ma v bb = 12v, gnd to v bb , v lin =0?18v microcontroller interface high-level input voltage (t xd , fault /t xe ) v ih 2.0 ? v reg +0.3 v low-level input voltage (t xd , fault /t xe ) v il -0.3 ? 0.8 v high-level input current (t xd , fault /t xe ) i ih -2.5 ? 0.4 a input voltage = 4.0v ~800 k ? internal adaptive pull-up low-level input current (t xd , fault /t xe ) i il -10 ? ? a input voltage = 0.5v ~800 k ? internal adaptive pull-up high-level input voltage (cs/lwake) v ih 2.0 ? v bb v through a current-limiting resistor low-level input voltage (cs/lwake) v il -0.3 ? 0.8 v note 1: internal current limited. 2.0 ms maximum recovery time (r lbus =0w, tx=0, v lbus =v bb ). 2: characterized, not 100% tested. 3: in power-down mode, normal lin recessive/dominant threshold is disabled. v wk ( lbus ) is used to detect bus activities. ? 2012-2014 microchip technology inc. ds20002298c-page 17 mcp2021a/2a high-level input current (cs/lwake) i ih ? ? 8.0 a input voltage = 0.8v reg ~1.3 m ? internal pull-down to v ss low-level input current (cs/lwake) i il ? ? 5.0 a input voltage = 0.2v reg ~1.3 m ? internal pull-down to v ss low-level output voltage (r xd ) v olrxd ? ? 0.2v reg vi ol =2ma high-level output voltage (r xd ) v ohrxd 0.8v reg ?? vi oh =2ma low-level output voltage (fault /t xe ) v olod ??1.0vi ol =4ma low-level output voltage (reset ) v olrst ??1.0vi ol =4ma bus interface high-level input voltage v ih (l bus ) 0.6 v bb ? ? v recessive state low-level input voltage v il (l bus )-8?0.4 v bb v dominant state input hysteresis v hys ? ? 0.175 v bb vv ih (l bus )?v il (l bus ) low-level output current i ol (l bus ) 40 ? 200 ma output voltage = 0.1 v bb , v bb = 12v pull-up current on input i pu (l bus )-180?-72a~30k ? internal pull-up @ v ih (l bus )=0.7v bb , v bb = 12v short circuit current limit i sc 50 ? 200 ma note 1 high-level output voltage v oh (l bus )0.8v bb ?v bb v driver dominant voltage v_ losup ??1.1vv bb =7.3v r load = 1000 ? v_ hisup ??1.2vv bb = 18v r load = 1000 ? input leakage current (at the receiver during dominant bus level) i bus _ pas _ dom -1 ? ? ma driver off v bus =0v v bb = 12v input leakage current (at the receiver during recessive bus level) i bus _ pas _ rec -20 ? 20 a driver off 8v < v bb < 18v 8v < v bus <18v v bus ? v bb leakage current (disconnected from ground) i bus _ no _ gnd -10 ? +10 a gnd device =v bb 0v < v bus <18v v bb = 12v leakage current (disconnected from v bb ) i bus _ no _ pwr -10 ? +10 a v bb =gnd 0 mcp2021a/2a ds20002298c-page 20 ? 2012-2014 microchip technology inc. 2.4 ac specifications ac characteristics electrical characteristics: unless otherwise indicated, all limits are specified for v bb = 6.0v to 18.0v; t a = -40c to +125c. parameter sym min typ max units conditions bus interface ? constant slope time parameters slope rising and falling edges t slope 3.5 ? 22.5 s 7.3v ? v bb ? 18v propagation delay of transmitter t transpd ??5.0st transpd =max. (t transpdr or t transpdf ) propagation delay of receiver t recpd ??6.0st recpd =max. (t recpdr or t recpdf ) symmetry of propagation delay of receiver rising edge w.r.t. falling edge t recsym -2.0 ? 2.0 s t recsym =max. (t recpdf ?t recpdr ) r rxd =2.4k ?? to v cc c rxd =20pf symmetry of propagation delay of transmitter rising edge w.r.t. falling edge t transsym -2.0 ? 2.0 s t transsym =max. (t transpdf ?t transpdr ) bus dominant time-out time t to ( lin )? 25 ?ms time to sample fault /t xe for bus conflict reporting t fault ??32.5st fault =max. (t transpd +t slope +t recpd ) duty cycle 1 @ 20.0 kbps 0.396 ? ? %t bit c bus ; r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? | 10 nf; 500 ? th rec ( max ) = 0.744 x v bb , th dom ( max )=0.581xv bb , v bb =7.0v?18v; t bit =50s. d1 = t bus _ rec ( min )/2 x t bit duty cycle 2 @ 20.0 kbps ? ? 0.581 %t bit c bus ; r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? | 10 nf; 500 ? th rec ( max ) = 0.284 x v bb , th dom ( max )=0.422xv bb , v bb =7.6v?18v; t bit =50s. d2 = t bus _ rec ( max )/2 x t bit duty cycle 3 @ 10.4 kbps 0.417 ? ? %t bit c bus ; r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? | 10 nf; 500 ? th rec ( max ) = 0.778 x v bb , th dom ( max )=0.616xv bb , v bb =7.0v?18v; t bit =96s. d3 = t bus _ rec ( min )/2 x t bit note 1: time depends on external capacitance and load. test condition: c reg = 4.7 f, no resistor load. 2: characterized, not 100% tested. ? 2012-2014 microchip technology inc. ds20002298c-page 21 mcp2021a/2a duty cycle 4 @ 10.4 kbps ? ? 0.590 %t bit c bus ; r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? | 10 nf; 500 ? th rec ( max ) = 0.251 x v bb , th dom ( max )=0.389xv bb , v bb =7.6v?18v; t bit =96s. d4 = t bus _ rec ( max )/2 x t bit voltage regulator bus activity debounce time t bdb 30 80 250 s bus activity to voltage regulator enabled t bactive 35 ? 200 s voltage regulator enabled to ready t vevr 300 ? 1200 s note 1 chip select to ready mode t csr ? ? 230 s chip select to power-down t cspd ? ? 330 s note 2 short circuit to shutdown t shutdown 20 ? 100 s reset timing v reg ok detect to reset inactive t rpu ??60s v reg not ok detect to reset active t rpd ??60s 2.5 thermal specifications parameter sym min typ max units test conditions specified temperature range t a -40 ? +125 ? c maximum junction temperature t j ??+150 ? c storage temperature range t a -65 ? +150 ? c recovery temperature ? recovery ?+140? ? c shutdown temperature ? shutdown ?+150? ? c short circuit recovery time t therm ?1.55.0ms thermal package resistances thermal resistance, 8l-pdip ? ja ? 89.3 ? ? c/w thermal resistance, 8l-soic ? ja ? 149.5 ? ? c/w thermal resistance, 8l-dfn ? ja ? 48 ? ? c/w thermal resistance, 14l-pdip ? ja ? 70 ? ? c/w thermal resistance, 14l-soic ? ja ? 90.8 ? ? c/w thermal resistance, 14l-tssop ? ja ? 100 ? ? c/w note 1: the maximum power dissipation is a function of t jmax , ? ja , and ambient temperature, t a . the maximum allowable power dissipation at an ambient temperature is p d =(t jmax ?t a ) ? ja . if this dissipation is exceeded, the die temperature will rise above 150 ? c and the mcp2021a/2a will go into thermal shutdown. 2.4 ac specifications (continued) ac characteristics electrical characteristics: unless otherwise indicated, all limits are specified for v bb = 6.0v to 18.0v; t a = -40c to +125c. parameter sym min typ max units conditions note 1: time depends on external capacitance and load. test condition: c reg = 4.7 f, no resistor load. 2: characterized, not 100% tested. mcp2021a/2a ds20002298c-page 22 ? 2012-2014 microchip technology inc. 2.6 typical performance curves note: unless otherwise indicated, v bb = 6.0v to 18.0v; t a = -40c to +125c. figure 2-2: typical i bbq vs. temperature ? 5.0v. figure 2-3: typical i bbto vs. temperature ? 5.0v. figure 2-4: typical i pd vs. temperature ? 5.0v. figure 2-5: typical i bbq vs. temperature ? 3.3v. figure 2-6: typical i bbto vs. temperature ? 3.3v. figure 2-7: typical i pd vs. temperature ? 3.3v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 80 100 120 140 160 180 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 i bbq (a) temperature ( | | c) v bb = 6v v bb = 12v v bb = 18v 50 60 70 80 90 -40 -25 -10 5 20 35 50 65 80 95 110 125 i bbtq (a) temperature ( | c) v bb = 6v v bb = 12v v bb = 18v 4 4.2 4.4 4.6 4.8 5 5.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 i pd (a) temperature ( | c) v bb = 6v v bb = 12v v bb = 18v 80 100 120 140 160 180 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 i bbq (a) temperature ( | c) v bb = 6v v bb = 18v v bb = 12v 50 60 70 80 90 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 i bbto (a) temperature ( | c) v bb = 6v v bb = 18v v bb = 12v 4 4.2 4.4 4.6 4.8 5 5.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( | c) i pd ( a ) v bb = 6v v bb = 18v v bb = 12v ? 2012-2014 microchip technology inc. ds20002298c-page 23 mcp2021a/2a figure 2-8: 5.0v v reg vs. i reg at v bb =12v. figure 2-9: 3.3v v reg vs. i reg at v bb =12v. 0 1 2 3 4 5 6 0 100 200 300 v reg (v) i reg (ma) -40c +125c +90c +25c 0 0.5 1 1.5 2 2.5 3 3.5 0 100 200 300 i reg (ma) v reg (v) -40c +125c +90c +25c mcp2021a/2a ds20002298c-page 24 ? 2012-2014 microchip technology inc. 2.7 timing diagrams and specifications figure 2-10: bus timing diagram figure 2-11: regulator cs/lwake timing diagram 0.95 v lbus 0.05 v lbus t transpdr t recpdr t transpdf t recpdf t xd l bus r xd internal t xd /r xd compare fault sampling t fault t fault fault /t xe output stable stable stable match match match match match hold value hold value 50% 50% 0.50 v bb 50% 50% 0.0v v reg l bus v wk ( lbus ) t vevr v reg - nom t bdb t bactive ? 2012-2014 microchip technology inc. ds20002298c-page 25 mcp2021a/2a figure 2-12: cs/lwake, regulator and reset timing diagram t cspd t csr cs/lwake v reg v reg - nom reset t rpu t vevr t rpd mcp2021a/2a ds20002298c-page 26 ? 2012-2014 microchip technology inc. 3.0 packaging information 3.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e nnn 8-lead soic (150 mil) (mcp2021a) example 2021a50e sn ^^1409 256 3 e xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) (mcp2021a) example yyww nnn xxxxxx xxxxxx pin 1 pin 1 2021a 500emd 1409 256 8-lead dfn (4x4x0.9 mm) (mcp2021a) example 2021a500 e/p ^^256 1409 3 e ? 2012-2014 microchip technology inc. ds20002298c-page 27 mcp2021a/2a package marking information (continued) 14-lead soic (.150?) (mc2022a) example 14-lead tssop (mcp2022a) mcp2022a 500e/sl ^^ 1409256 3 e yyww nnn xxxxxxxx 2022a500 1409 256 14-lead pdip (300 mil) (mcp2022a) example example mcp2022a 500e/p ^^ 1409256 3 e mcp2021a/2a ds20002298c-page 28 ? 2012-2014 microchip technology inc. 8-lead plastic dual flat, no lead package (md) C 4x4x0.9 mm body [dfn] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technology drawing c04-131e sheet 1 of 2 ? 2012-2014 microchip technology inc. ds20002298c-page 29 mcp2021a/2a 8-lead plastic dual flat, no lead package (md) C 4x4x0.9 mm body [dfn] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technology drawing c04-131e sheet 2 of 2 mcp2021a/2a ds20002298c-page 30 ? 2012-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2012-2014 microchip technology inc. ds20002298c-page 31 mcp2021a/2a b a for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing no. c04-018d sheet 1 of 2 8-lead plastic dual in-line (p) - 300 mil body [pdip] eb e a a1 a2 l 8x b 8x b1 d e1 c c plane .010 c 12 n note 1 top view end view side view e mcp2021a/2a ds20002298c-page 32 ? 2012-2014 microchip technology inc. microchip technology drawing no. c04-018d sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 8-lead plastic dual in-line (p) - 300 mil body [pdip] units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a - - .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb - - .430 bsc: basic dimension. theoretically exact value shown without tolerances. 3. 1. protrusions shall not exceed .010" per side. 2. 4. notes: -- dimensions d and e1 do not include mold flash or protrusions. mold flash or pin 1 visual index feature may vary, but must be located within the hatched area. significant characteristic dimensioning and tolerancing per asme y14.5m e datum a datum a e b e 2 b e 2 alternate lead design (vendor dependent) ? 2012-2014 microchip technology inc. ds20002298c-page 33 mcp2021a/2a note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging mcp2021a/2a ds20002298c-page 34 ? 2012-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2012-2014 microchip technology inc. ds20002298c-page 35 mcp2021a/2a mcp2021a/2a ds20002298c-page 36 ? 2012-2014 microchip technology inc. n e1 d note 1 12 3 e c eb a2 l a a1 b1 be ? 2012-2014 microchip technology inc. ds20002298c-page 37 mcp2021a/2a note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging mcp2021a/2a ds20002298c-page 38 ? 2012-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2012-2014 microchip technology inc. ds20002298c-page 39 mcp2021a/2a mcp2021a/2a ds20002298c-page 40 ? 2012-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2012-2014 microchip technology inc. ds20002298c-page 41 mcp2021a/2a note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging mcp2021a/2a ds20002298c-page 42 ? 2012-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2012-2014 microchip technology inc. ds20002298c-page 43 mcp2021a/2a appendix a: revision history revision c (july 2014) the following is the list of modifications: 1. updated section 1.6 ?typical applications? with values used during esd tests. 2. minor typographical corrections. 3. updated 8-lead pdip package. revision b (december 2013) the following is the list of modifications: 1. removed two notes in ac specifications . 2. updated figure 1-3 . 3. added pull-up to fault /t xe pin in the pin description and typical applications. 4. revised product identification examples for soic package. revision a (march 2012) ? original release of this document. mcp2021a/2a ds20002298c-page 44 ? 2012-2014 microchip technology inc. product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp2021a: lin transceiver with voltage regulator mcp2021at: lin transceiver with voltage regulator (tape and reel) mcp2022a: lin transceiver with voltage regulator mcp2022at: lin transceiver with voltage regulator (tape and reel) voltage: 330 = 3.3v 500 = 5.0v temperature range: e = -40c to +125c package: md = 8ld plastic dual flat, no lead ? 4x4x0.8 mm body p = 8ld/14ld plastic dual in-line ? 300 mil body sn = 8ld plastic small outline ? narrow, 3.90 mm body sl = 14ld plastic small outline ? narrow, 3.90 mm body st = 14ld plastic thin shrink small outline ? 4.4 mm body part no. ?x /xx package voltage device examples: a) mcp2021a-330e/md: 3.3v, 8-lead dfn package b) mcp2021a-500e/md: 5.0v, 8-lead dfn package c) mcp2021at-330e/md: 3.3v, 8-lead dfn package, tape and reel d) mcp2021at-500e/md: 5.0v, 8-lead dfn package, tape and reel e) mcp2021a-330e/p: 3.3v, 8-lead pdip package f) mcp2021a-500e/p: 5.0v, 8-lead pdip package g) mcp2021a-330e/sn: 3.3v, 8-lead soic package h) mcp2021at-330e/sn: 3.3v, 8-lead soic package, tape and reel i) mcp2021a-500e/sn: 5.0v, 8-lead soic package j) mcp2021at-500e/sn: 5.0v, 8-lead soic package, tape and reel a) mcp2022a-330e/p: 3.3v, 14-lead pdip package b) mcp2022a-500e/p: 5.0v, 14-lead pdip package c) mcp2022a-330e/sl: 3.3v, 14-lead soic package d) mcp2022at-330e/sl: 3.3v, 14-lead soic package, tape and reel e) mcp2022a-500e/sl: 5.0v, 14-lead soic package f) mcp2022at-500e/sl: 5.0v, 14-lead soic package, tape and reel g) mcp2022a-330e/st: 3.3v, 14-lead tssop package h) mcp2022at-330e/st: 3.3v, 14-lead tssop package, tape and reel i) mcp2022a-500e/st: 5.0v, 14-lead tssop package j) mcp2022at-500e/st: 5.0v, 14-lead tssop package, tape and reel ?x temperature range ? 2012-2014 microchip technology inc. ds20002298c-page 45 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012-2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63276-403-4 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == ds20002298c-page 46 ? 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